Implementation of Baugh-Wooley Multiplier Based on Soft-Core Processor
نویسندگان
چکیده
منابع مشابه
Design of Low Power Baugh Wooley Multiplier Using CNTFET
Multipliers are one of the most important components in microprocessors and DSP processors [9]. Baugh Wooley is one among them and it is an array multiplier. Array multipliers have a more regular layout and it presents high speed performance. The paper deals with the design of a Baugh Wooley multiplier using Carbon Nanotube Field Effect Transistor (CNTFET). A Verilog-A formulation of the Stanfo...
متن کاملFPGA Implementation of High Speed Baugh-Wooley Multiplier using Decomposition Logic
The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared wi...
متن کاملMany-Core Processor based Pseudo-Stateful Traffic Multiplier
Benchmark of high performance network devices relies on high throughput traffic generator. The traffic generators are software based or dedicated hardware based. The software based traffic generators are usually running on relatively cheap commercial computer in a flexible, low cost way but suffering from poor performance. The hardware based generators can provide more precisely measured heavy ...
متن کاملEfficient Multiplication Carry-Save on-The Fly Correction with Advanced Vedic and Baugh-Wooley Methodologies
The main objective of the proposed work is implementing the 32 bit Vedic and Baugh-Wooley multiplication operation with Carry-Save methodology to reduce the average time and delay of operations. This system contain a high speed low power digital multiplier by using advantage of Vedic multiplication algorithms with a very efficient leakage control technique called multiple channel conventional m...
متن کاملImplementation of Data Compression Algorithms on FPGA using Soft-core Processor
With the increase in the requirement of online real time data, data compression algorithms are to be implemented for increasing throughput. This paper describes the methods of creating dedicated hardware which can receive uncompressed data as input and transmit compressed data at the output terminal. This method uses FPGA for the same, wherein the hardware part has been created using Xilinx Emb...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IOSR Journal of Engineering
سال: 2013
ISSN: 2278-8719,2250-3021
DOI: 10.9790/3021-031030107